HW-in-the-Loop with SystemC

Last week, I was at a multicore event, and some presentations reminded me of my MS thesis work back in 2008-2010. In this post, I’d like to provide material produced during my MS thesis work with my professors Arda Yurdakul and Alper Sen with a short introduction.

The work was about introducing the HW-in-the-Loop (HiL) method to the HW-SW co-design domain. HiL is about integrating virtual (simulated) environments with real environments to enable useful scenarios such as testing virtual models under development on real test beds, testing real devices with virtual test beds etc.

Integration of virtual subsystems and real subsystems using hybrid channels which are real and virtual
HW-in-the-Loop Simulation with SystemC

A central concept we developed was hybrid channels, which uses a regular SystemC channel to address the issue of integrating the simulation environment to the real world. This allows very straightforward, low effort and low risk switching to/from a HiL setup. Additionally, since SystemC uses channels also among internal modules, the HiL can be easily introduced in different places of the model.

We addressed additional issues to achieve our goal, you can read more about them in the linked material:

  • Binding the simulation clock to the wall clock.
  • Improving platform’s real-time determinism to ensure accurate timing of the model.
  • Handling concurrent outputs from the non-concurrently executing model
  • Introducing external events into the simulation event queue

We published our results in some conferences and a journal:

Additionally, we were granted a patent, unfortunately only in the Turkish market, due to an issue about transferring the initial patent filing from my company to my university.

You can also access the full thesis and the defense presentation.

I’d like to thank my professors for their guidance again. Always interested in your feedback on the work.

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